1. Field of the Invention
This invention relates to the field of computing or data processing, and more specifically, to an IEEE 1394-to-ATA interface unit having two small size First In First Out (FIFO) queues that are associated with both a receive data path and a transmit data path.
2. Description of the Related Art
As used herein, the term ATA refers to an interface specification for Integrated Drive Electronics (IDE) drives; for example, hard disk mass storage devices having a built-in controller. IDE drives often connect via an ATA interface, such as a flat ATA ribbon cable, to an IDE host adapter that plugs into an expansion slot within a personal computer.
The use of transmit and receive FIFOs in a data processing system is known. For example, U.S. Pat. No. 5,136,582 to Firoozmand describes, relative to FIG. 5, an output buffer (120) that is connected to a DMA controller (124) by way of a receive path that includes, in series, a physical RCV FIFO, a logical SRAM receive-FIFO, and a physical RCV FIFO (175), and a transmit path that includes, in series, a physical XMT FIFO, one but preferably four logical transmit FIFOs (177), and a physical XMT FIFO. U.S. Pat. No. 5,210,749 to Firoozmand is generally similar.
U.S. Pat. No. 5,572,676 to Ohnishi teaches the use of a transmission FIFO and a reception-FIFO U.S. Pat. No. 5,644,577 also teaches the use of FIFOs to buffer transmit and receive portions of a data frame, wherein the data-frame is stretched or compressed, as necessary, to match available data to the FIFO buffers.
U.S. Pat. No. 5,535,197 to Cotton is of general interest in that it describes a buffered communication switch for use in an ATM system having a switching-module that includes a shared memory buffer. When a data cell is received, the cell""s header is translated to determine cell routing and cell priority. The cell is then stored at a vacant address in a shared memory buffer, as the cell""s address is placed in a FIFO queue at the appropriate exit port. When time is available for transmission on an outgoing link, the data cell corresponding to the address that is at the front of the exit port""s queue is transmitted toward its destination. U.S. Pat. No. 5,610,914 also teaches the use of a shared memory buffer for an ATM switching system and includes address pointers that are stored in FIFOs.
U.S. Pat. No. 5,488,694 to McKee et at is also noted for its use of a FIFO register.
The above-mentioned patents are incorporated herein by reference for the purpose of indicating the background of the invention and/or as illustrating the state of the art.
While the above-noted patents are of general utility for their stated purposes, the need remains in the art for a data processing system that is especially constructed and arranged to process the continuous asynchronous transmission and reception of relatively small-size data packets, while at the same time, enabling the asynchronous transmission and reception of a half-duplex stream of relatively large size data packets.
This invention relates to a data processing system that is especially constructed and arranged to process the continuous asynchronous transmission and reception of relatively small-size data packets while, at the same time, enabling the asynchronous transmission and reception of a half-duplex stream of relatively large-size data packets. By way of example only, small-size data packets comprise about 4 quadlets of data in size (i.e., about 16-bytes of data), whereas large-size data packets are of a size that is about 2K plus 16-bytes of data.
In order to accomplish two-way data transmit/receive functions in an IEEE 1394-to-ATA interface unit, a relatively small-size receive FIFO is associated with one data path, and a relatively small-size transmit FIFO is associated with a second data path. In the operation of the invention, the small-size data packets are directly handled by the FIFOs, whereas these same FIFOs operate to store the time order, or the as-received queue, of the large-size transmit and receive data packets, as the data content of these large-size data packets is stored in a larger data bank, or buffer, that is capable of both a data transmit and a data receive function. This invention optimizes the size of the two FIFOs and the data bank for a given size of a relatively large size core data storage that is associated therewith.
In an embodiment of the invention, the two above-mentioned FIFOs each comprised 64 individually addressable quadlets (a quadlet equals 4 bytes) of RAM data storage, the data bank or buffer comprised a first RAM data bank 0 and a second RAM data bank 1, each of which comprises 512 quadlets of data storage, and the two FIFOs and two data banks were associated with core data storage that comprised 512K bytes of data storage. While two FIFOs are required for proper operation in accordance with this invention, the number of data banks is not critical.
The small-size data packets are received or transmitted asynchronously; that is, the small-size data packets are received without a regular or a predictable time relationship following the execution of an I/O request. Since the large-size data packets are received or transmitted asynchronous half-duplex (that is, in only one direction at a time), the headers of the large-size data packets can be FIFO stored, as the corresponding data content is stored in a data bank. As a result of the use of these two FIFOs, two messages going in either direction can be queued up.
In the operation of the invention, the headers of half-duplex large-size data packets are always obtained from the transmit FIFO for a transmit operation, and are always placed in the receive FIFO for a receive-operation. Any given header identifies, addresses, or points to the storage location in the data bank whereat data corresponding to the given header will be found for a transmit operation, or the given header contains the address of the storage location in a data bank whereat the data corresponding to the given header is stored for a receive operation.
For example, in an asynchronous half-duplex transmit-operation involving a large-size data packet, the packet""s header is first fetched from the head end storage position within the transmit FIFO, the address that is within this fetched header is read, the data at this address is fetched from a data bank, and the transmission is completed. In a receive operation, the data portion of an asynchronously received half-duplex large-size data packet is placed in a given storage location within a data bank, and the tail end storage location of the receive FIFO is loaded with a header that contains the address of this given storage location, whereupon the receive operation is completed.
As a feature of the invention, a special segment of RAM is provided for use as a general purpose scratch pad. For example, this special segment RAM can be set up as 16 different Operational Request Block (ORB) locations, each location of which can be used to store a 32-byte ORB. The header for each such ORB is placed in the receive FIFO, whereas the data content of the ORB itself is placed in this special segment RAM.
The above-mentioned ORBs are the means by which a request (for example, a read request or a write request), is communicated to a target mass storage device. For example, each 32-byte ORB contains a fixed format.
The above-mentioned bank 0 storage, bank 1 storage, receive FIFO storage, transmit FIFO storage, and special segment storage are preferably all contained within a buffer RAM that is partitioned to provide these dedicated storage areas. A buffer manager provides an interface to the buffer RAM for a link module, for an auto sequencer, and for microcontroller interface modules.
The receive FIFO receives small-size data packets from a link module, and only one link module has access to the receive-FIFO at any given time. All such small-size data packets are serviced in the order that they are received.
The transmit FIFO is used to send large-size data packets to a link module, and only one link module can communication with the transmit FIFO at any given time. All large-size data packets are transmitted in time order.
An object of this invention is to provide an interface unit that operates as a bridge between the IEEE-1394-port of a device, such as a host computer and the ATA-port of an ATA I/O device such as a mass storage device.
Another object of this invention is to provide an interface unit bridge that enables an ATA-compatible I/O device to be located a relatively long distance from a 1394-compatible host by making use of the desirable operating characteristics of a 1394 cable to enable an interface unit and the I/O device (a target device) to be located at a relatively long distance from the host; i.e., at a distance that is not supported by the operational characteristics of an ATA interface.
Another object of this invention is to provide a method and an apparatus providing for communication of small byte-size packets and large byte-size packets from a first to a second port, including FIFO storage and buffer storage. The reception of a small byte-size packet at the first port causes the small byte-size packet to be stored in a tail end storage location of the FIFO storage. The reception of a large byte-size packet at the first port causes the large byte-size packet to be stored in an addressable storage location of the buffer storage, and causes an address of this addressable storage location to be stored in a tail-end storage location of the FIFO storage. The subsequent presence of the small byte-size packet in a head end storage location of the FIFO storage causes the small byte-size packet to be transmitted to the second port. The subsequent presence of the address of the addressable storage location in a head end storage location of the FIFO storage causes the large byte-size packet to be fetched from the buffer byte storage and causes the large byte-size packet to be transmitted to the second port.
These and other objects, features and advantages of this invention will be apparent to those of skill from the following detailed description, which description makes reference to the drawing.
Another object of this invention is to provide a means for the large-sized packets to be handled at a different rate than the small-sized packets, thus allowing control streams to run asynchronous to data streams.